For decades, India excelled at writing the software that powered the world’s computers but remained almost entirely dependent on other countries for the chips inside them. Every smartphone, fighter aircraft, satellite, electric vehicle, telecom network and artificial intelligence system relied on semiconductors designed and manufactured largely outside India’s borders.

That dependence has become one of the country’s biggest strategic vulnerabilities.

Today, India is attempting to change that.

How the India Semiconductor Mission Began

What began as an industrial policy is steadily evolving into a national technology mission—one that seeks not merely to manufacture chips, but to build an ecosystem spanning design, fabrication, advanced packaging, materials, equipment and skilled talent. If successful, it could reshape India’s manufacturing landscape and strengthen its position in a global technology race increasingly defined by semiconductor capabilities.

The launch of the India Semiconductor Mission (ISM) marked a turning point. Rather than offering isolated incentives, the government adopted a mission-driven approach aimed at creating an end-to-end semiconductor ecosystem. The objective extends beyond attracting investment; it is about ensuring technological sovereignty in a world where access to chips increasingly determines economic resilience and national security.

The Design Linked Incentive (DLI) scheme has been an important catalyst. We are seeing some early success. At the same time, there is also an evolutionary factor at play. Engineers who moved abroad 20–25 years ago are now at a stage where they have both the experience and financial capacity to take entrepreneurial risks. Many also want to return to India–says Neelkanth Mishra, in an interview with EdPublica.

Why semiconductors matter

Semiconductors are often described as the “brains” of modern electronics, but their strategic significance runs far deeper.

Every sector that governments now classify as critical—artificial intelligence, defence, space, telecommunications, medical devices, automobiles, renewable energy and industrial automation—depends on increasingly sophisticated chips.

The COVID-19 pandemic exposed how vulnerable global supply chains had become. Factory shutdowns in one part of the world disrupted automobile production thousands of kilometres away. Geopolitical tensions further highlighted the risks of concentrating semiconductor manufacturing in only a handful of countries.

For India, which imports billions of dollars’ worth of electronic components every year, the lesson was unmistakable: technological ambition cannot rest entirely on imported hardware.

Building the foundation

Recognising this challenge, the government launched India Semiconductor Mission 1.0, backed by a financial incentive programme worth ₹76,000 crore. It represented India’s first coordinated attempt to build semiconductor manufacturing capabilities within the country.

The mission was designed to support multiple segments simultaneously:

>> silicon wafer fabrication plants;

>> assembly, testing, marking and packaging (ATMP) facilities;

>> Outsourced Semiconductor Assembly and Test (OSAT) units;

>> compound semiconductor manufacturing;

>> semiconductor design through the Design Linked Incentive (DLI) Scheme.

Rather than relying on a single mega-project, policymakers attempted to create an ecosystem in which manufacturing, design, packaging and supply chains could evolve together.

From policy announcements to factories

One of the biggest criticisms of India’s earlier electronics programmes was that announcements often outpaced execution.

This time, the picture is beginning to look different.

Approved semiconductor projects now represent cumulative investment commitments exceeding ₹1.64 lakh crore, spread across multiple states. According to the Ministry of Electronics and Information Technology, the approved portfolio now covers fabrication facilities, packaging plants and compound semiconductor manufacturing, reflecting a broader industrial base than initially envisioned.

The most visible milestone has been the commencement of commercial production at Micron Technology’s advanced semiconductor packaging facility in Gujarat, widely regarded as the first major operational success under the mission.

Several other large projects—including those led by Tata Electronics, Kaynes Semicon, and the Tata-PSMC semiconductor fabrication project at Dholera—have moved into advanced stages of construction and are expected to enter commercial production soon. Together, they represent India’s first serious attempt to establish domestic silicon manufacturing at scale.

Equally significant is the geographical spread.

Instead of concentrating semiconductor manufacturing in one industrial cluster, projects are now emerging across Gujarat, Rajasthan and other states, creating the beginnings of a distributed semiconductor manufacturing network.

Manufacturing is only one piece of the puzzle

Building chips requires far more than fabrication plants.

A modern semiconductor ecosystem depends on hundreds of specialised suppliers producing chemicals, gases, ultra-pure materials, precision equipment, packaging technologies and printed circuit boards (PCBs).

Recognising these gaps, the government has started extending policy support beyond chip fabrication.

A recent example is the foundation of advanced PCB manufacturing projects worth about ₹6,750 crore in Jewar, Uttar Pradesh. These facilities are expected to manufacture high-density multilayer PCBs—including advanced 20-22 layer boards—that India has traditionally imported in large quantities.

Reducing imports of such critical components strengthens the broader electronics manufacturing ecosystem while creating domestic capabilities that extend well beyond semiconductor fabrication itself.

Design remains India’s strongest advantage

While fabrication receives most public attention, India already possesses one major strength: semiconductor design.

Thousands of engineers employed by global companies already design chips from Indian engineering centres. The challenge has been converting this design talent into domestic intellectual property.

The Design Linked Incentive (DLI) Scheme attempts to bridge that gap.

According to government data, the programme has supported dozens of chip design projects, enabled successful tape-outs, encouraged patent filings and provided advanced chip-design tools to more than 100 companies while training a growing pool of specialised semiconductor engineers.

Moving from outsourced engineering services towards Indian-owned semiconductor intellectual property could prove just as significant as establishing fabrication plants.

The next chapter: ISM 2.0

If the first phase focused on attracting semiconductor manufacturing, the next phase aims to deepen India’s role across the entire value chain.

Announced in the Union Budget 2026-27, India Semiconductor Mission 2.0 shifts attention towards areas where India still depends heavily on imports.

The new phase proposes support for:

>> semiconductor manufacturing equipment;

>> specialty materials and chemicals;

>> indigenous semiconductor intellectual property;

>> advanced packaging technologies;

>> compound semiconductors;

>> industry-led research and training centres.

The underlying philosophy is straightforward: long-term self-reliance cannot be achieved by importing all the machinery, chemicals and specialised materials required to manufacture chips.

Instead, India aims to build capabilities throughout the production chain—from research laboratories to finished semiconductor products.

Recent reports indicate that the government is also preparing a substantially larger financial commitment for ISM 2.0 as it expands beyond manufacturing incentives into ecosystem development.

Strategic partnerships without strategic dependence

India’s semiconductor strategy has deliberately combined domestic capability building with international collaboration.

Leading companies from the United States, Taiwan, Japan and South Korea have become partners in India’s emerging semiconductor ecosystem, bringing technology, manufacturing expertise and investment.

This reflects a broader policy shift.

Rather than attempting complete technological isolation, India is seeking trusted international partnerships while gradually strengthening indigenous capabilities in manufacturing, design and supply chains.

In an increasingly fragmented global technology landscape, diversification itself has become a strategic asset.

The road ahead remains difficult

Despite visible progress, India’s semiconductor journey is still in its early stages.

Chip fabrication demands extraordinary precision, massive capital investments, reliable infrastructure and uninterrupted supplies of ultra-pure water, electricity and specialised materials. Success also depends on building a workforce capable of operating some of the world’s most sophisticated manufacturing facilities.

Moreover, semiconductor manufacturing is measured in decades, not election cycles.

Countries that dominate the industry today invested consistently over many years before becoming global leaders.

India therefore faces the challenge of maintaining policy continuity while ensuring that announced projects translate into commercially competitive production.

A larger national ambition

The significance of India’s semiconductor mission extends well beyond electronics manufacturing.

Every fabrication facility commissioned, every packaging unit established and every design company supported reduces import dependence, creates highly skilled employment and strengthens India’s position within global technology supply chains.

For a country seeking greater strategic autonomy, semiconductor capability is increasingly becoming as important as energy security or defence preparedness.

The first phase of the mission has established the initial building blocks. The second phase aims to strengthen the ecosystem beneath them.

Whether India ultimately becomes a major global semiconductor hub will depend not on a single factory or policy announcement, but on its ability to sustain investment, develop talent, encourage innovation and build an integrated value chain over the coming decade.

After years of watching the global semiconductor revolution from the sidelines, India has entered the race. The challenge now is to ensure that today’s investment commitments become tomorrow’s manufacturing capability—and eventually, technological leadership.

Researchers at the Massachusetts Institute of Technology (MIT) have developed a new ultra-efficient chip that enables tiny autonomous robots to generate detailed 3D maps of their surroundings in real time while consuming only a fraction of the power required by existing systems.

The new MIT robot navigation chip, called Gleanmer, could help small drones and robots safely navigate complex environments, from industrial heating and ventilation systems to confined inspection spaces where battery life and computing resources are limited.

According to the researchers, the chip consumes just 6 milliwatts of power—roughly the same amount needed to run a single LED—while constructing detailed 3D maps for navigation.

The findings were recently presented at the IEEE Very Large-Scale Integrated Circuits Symposium.

Designed for battery-powered robots

Autonomous robots rely on 3D maps to understand their surroundings and avoid obstacles. However, generating these maps typically requires significant computing power and memory, making the process difficult for small, battery-powered devices.

The MIT team tackled this challenge by combining a highly efficient mapping algorithm with custom-designed hardware that minimizes memory usage and energy consumption.

“This paper showcases a key example of how you can leverage co-design of the algorithm and hardware to really push energy efficiency,” Vivienne Sze, professor in MIT’s Department of Electrical Engineering and Computer Science and senior author of the study, said in a media statement.

“While there has been a lot of work looking into compact 3D maps, what stands out about this work is that it also ensures that the process to generate those maps is as efficient as possible. Our chip allows you to store very large maps in a very small space, and do it in a very energy efficient manner,” she added.

Replacing cubes with ‘Gaussian blobs’

Traditional mapping systems represent environments using millions of cube-shaped units known as voxels. These structures require substantial memory and processing power.

Instead, the MIT researchers employed a technique that represents objects using flexible ellipsoid-shaped structures known as Gaussians.

Because these Gaussian representations can adapt to the shape of real-world objects more efficiently, the system requires far less memory than conventional approaches while still preserving detailed information about obstacles and free space.

The chip uses a mapping algorithm developed by the researchers called GMMap, which can generate accurate 3D maps from depth images in a single pass, eliminating the need to repeatedly process and store large image datasets.

“At any point in time, we only need to store a few pixels in memory, which significantly reduces the memory footprint our algorithm requires,” co-lead author Peter Zhi Xuan Li said.

Improving efficiency through hardware-software co-design

As robots move through an environment, they often observe the same object from multiple viewpoints, creating overlapping representations that can increase map size.

To address this, the researchers developed a technique that merges overlapping Gaussian representations directly, without revisiting the original image data. This further reduces memory requirements and power consumption.

The chip also keeps frequently used map data in small on-chip memory units located close to the processing hardware, reducing the need to access more energy-intensive external storage.

“By having a dedicated memory that just stores the objects you’ve seen in the previous few frames, you can access the data much more efficiently,” co-lead author Zih-Sing Fu said.

Potential uses beyond robotics

The researchers tested the chip using a range of existing 3D environments and live data streams from an iPhone camera. In these experiments, Gleanmer generated detailed maps in real time while consuming only about 2.5% of the power required by the best existing map-construction chips.

The team believes the technology could be useful not only for autonomous robots and drones but also for lightweight augmented reality headsets, particularly in applications such as medical training, repair work, and industrial assembly.

“We reduce the memory consumption by making sure the algorithm is efficient. Then we accelerate the workload that is performed by that efficient algorithm, so in the end, our chip is as efficient as possible,” Li said.

Researchers now plan to further improve the technology by bringing processing components closer to sensors and exploring additional applications, including AI systems that need to analyse complex engineering schematics.

At 20:30 hours IST yesterday, NASA’s Johnson Space Center in Houston, Texas held a live event their engineers, scientists, the astronaut corps and the media attended. The space agency officially announced the crew of Artemis III, the agency’s next human space exploration mission, paving the way for humanity’s planned return to the moon in 2028, over fifty years after the Apollo program.

Half-way through the hour-long presentation, Jared Isacson, the NASA administrator, walked to the dais to announce the all-men crew of Artemis III: NASA mission commander Randy Bresnik, mission specialists Andre Douglas and Frank Rubio, and European Space Agency pilot Luca Parmitano, an Italian national. 

Three of the astronauts excluding Douglas, a US Coast Guard reserve, are both spaceflight and military veterans. Bresnik, a US marine colonel and test pilot clocking 7,000 hours, commanded the International Space Station. So did Parmitano, the first Italian commander of the station, and who survived a 2013 spacewalk when water abruptly filled his helmet and had an asteroid named after him. Rubio, a US army helicopter pilot, holds the record for the longest time spent in space. 

Screengrab from the YouTube livestream of the event at NASA Johnson Space Center, Houston, Texas. Credit: NASA

Mission timeline

The mission could take off in the second-half of 2027. Originally,  NASA planned Artemis III to be the first soft-landing lunar mission since 1972’s Apollo 17, with a slated launch date in 2028. However, in March, the agency updated mission timelines, with the mission relegated for testing its mission critical docking mechanism, ahead of Artemis IV’s planned soft-landing that year.

The crew will fly aboard a Space X Orion capsule into low-earth orbit. Unlike its predecessor, Artemis III won’t leave earth orbit and conduct a flyby past the moon. Instead, it will test life support systems and docking with Artemis’ era lunar landers, built by private space companies Space X and Blue Origin, the Starship Human Landing System (HLS) and the Blue Moon respectively. In addition, Artemis III will carry on science experiments, including using instrumentation to test effects of atmospheric drag upon the spacecraft, amidst hostile space weather.

The Apollo and Artemis-era lunar landers drawn to scale. Credit: NASA

Lunar landers 

There has been skepticism whether the Blue Moon lunar lander’s launch schedule would be affected, in the aftermath of last week’s mishap involving New Glenn, the flagship rocket of Jeff Bezos-owned Blue Origin, exploding during a hot-static test ahead of its slated launch of Amazon’s satellites. The explosion destroyed the company’s custom-developed launchpad at Cape Canaveral Space Force Station in Florida. However, the company CEO, David Limp, posted on X, they’ll return to full-swing operations latest before the end of this year.

Whereas Starship HLS, the other lunar lander design, will feature a variant of the Starship rocket, with the latter design being still tested over repeated space flights in the past year. 

Either lunar landers designed to ferry astronauts from lunar orbit to the surface, and back. In a future Artemis mission, the astronauts, who will ride aboard Space X’s Orion crew module from earth, will dock with the lander in lunar orbit, before transferring to the lander module. 

It’s unclear which lander design’s slated to make the soft-landing attempt in Artemis IV.